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1 ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1116, rev. b CAT24C03/05 2-kb and 4-kb i 2 c serial eeprom with partial array write protection pin configuration functional symbol features supports standard and fast i 2 c protocol 1.8 v to 5.5 v supply voltage range 16-byte page write buffer hardware write protection for upper half of memory schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda). low power cmos technology 1,000,000 program/erase cycles 100 year data retention industrial temperature range rohs-compliant 8-lead pdip, soic, and tssop, 8-pad tdfn and 5-lead tsot-23 packages. pdip (l) soic (w) tssop (y) tdfn (vp2) v cc v ss sd a scl wp CAT24C03 cat24c05 a 2 , a 1 , a 0 device description the CAT24C03/cat24c05 is a 2-kb/4-kb cmos serial eeprom device organized internally as 16/32 pages of 16 bytes each, for a total of 256x8/512x8 bits. these devices support both standard (100khz) as well as fast (400khz) i 2 c protocol. data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a page write buffer, and then writing all data to non-volatile memory in one internal write cycle. data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. write operations can be inhibited for upper half of memory by taking the wp pin high. external address pins make it possible to address up to eight CAT24C03 or four cat24c05 devices on the same bus. 8 7 6 5 v c c wp scl sda a 2 / a 2 nc / a 0 cat24c05 / 03 a 1 / a 1 v ss 1 2 3 4 for the location of pin 1, please consult the corresponding package drawing. pin functions a 0 , a 1 , a 2 device address inputs sda serial data input/output scl serial clock input wp write protect input v cc power supply v ss ground nc no connect * catalyst carries the i 2 c protocol under a license from the philips corporation. tsot-23 (td) 5 4 wp v cc scl v ss sda 1 2 3 for ordering information details, see page 17.
CAT24C03/05 2 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings (1) storage temperature -65c to +150c voltage on any pin with respect to ground (2) -0.5 v to +6.5 v reliability characteristics (3) symbol parameter min units n end (4) endurance 1,000,000 program/ erase cycles t dr data retention 100 years d.c. operating characteristics v cc = 1.8 v to 5.5 v, t a = -40c to 85c, unless otherwise speci?ed. symbol parameter test conditions min max units i ccr read current read, f scl = 400 khz 1 ma i ccw write current write, f scl = 400 khz 1 ma i sb standby current all i/o pins at gnd or v cc 1 a i l i/o pin leakage pin at gnd or v cc 1 a v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc 2.5 v, i ol = 3.0 ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0 ma 0.2 v pin impedance characteristics v cc = 1.8 v to 5.5 v, t a = -40c to 85c, unless otherwise speci?ed. symbol parameter conditions max units c in (3) sda i/o pin capacitance v in = 0 v 8 pf c in (3) input capacitance (other pins) v in = 0 v 6 pf i wp (5) wp input current v in < v ih, v cc = 5.5 v 200 a v in < v ih, v cc = 3.3 v 150 v in < v ih, v cc = 1.8 v 100 v in > v ih 1 note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci - ?cation is not implied. exposure to any absolute maximum rating for extended periods may af fect device performance and reliability. (2) the dc input voltage on any pin should not be lower than -0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than -1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropriate aec-q100 and jedec test methods. (4) page mode, v cc = 5 v, 25c (5) when not driven, the wp pin is pulled down to gnd internally. for improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull-down reverts to a weak current source.
CAT24C03/05 3 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice a.c. characteristics (1) v cc = 1.8 v to 5.5 v, t a = -40c to 85c. symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f (2) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to data out valid 3.5 0.9 s t dh data out hold time 100 100 ns t i (2) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 2.5 s t wr write cycle time 5 5 ms t pu (2, 3) power-up to ready mode 1 1 ms note: (1) test conditions according to a.c. test conditions table. (2) tested initially and after a design or process change that affects this parameter. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3 ma (v cc 2.5 v); i ol = 1 ma (v cc < 2.5 v); c l = 100 pf
CAT24C03/05 4 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice power-on reset (por) the CAT24C03/05 incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the CAT24C03/05 device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por feature protects the device against brown-out failure following a temporary loss of power. pin description scl: the serial clock input pin accepts the serial clock generated by the master. sda: the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a0, a1 and a2: the address inputs set the device ad - dress when cascading multiple devices. when not driven, these pins are pulled low internally. wp: the write protect input pin inhibits the write opera - tions for upper half of memory, when pulled high. when not driven, this pin is pulled low internally. functional description the CAT24C03/05 supports the inter-integrated circuit (i 2 c) bus data transmission protocol, which de?nes a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data ?ow is controlled by a master device, which generates the serial clock and all start and stop conditions. the CAT24C03/05 acts as a slave device. master and slave alternate as either transmitter or receiver. i 2 c bus protocol the i 2 c bus consists of two wires, scl and sda. the two wires are connected to the v cc supply via pull-up resistors. master and slave devices connect to the 2- wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to transmit a 0 and releases it to transmit a 1. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high . an sda transition while scl is high will be interpreted as a start or stop condition (figure 1). the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a wake-up call to all receivers. absent a start, a slave will not respond to commands. the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8-bit serial slave address. for normal read/write opera - tions, the ?rst 4 bits of the slave address are ?xed at 1010 (ah). the next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. the last bit of the slave address, r/ w , speci?es whether a read (1) or write (0) opera - tion is to be performed. the 3 address space extension bits are assigned as illustrated in figure 2. a 2 , a 1 and a 0 must match the state of the external address pins, and a 8 (cat24c05) is internal address bit. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9 th clock cycle (figure 3). the slave will also acknowledge the address byte and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. as long as the master acknowledges the data, the slave will continue transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by issuing a stop condition. bus timing is illustrated in figure 4.
CAT24C03/05 5 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 3. acknowledge timing figure 2. slave address bits 1 8 9 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack delay ( t aa ) ack setup ( t su:dat ) start condition stop condition sda scl figure 1. start/stop conditions figure 4. bus timing t high scl sda in sda out t low t f t low t r t buf t su:s to t su:d at t hd:d at t hd:s ta t su:s ta t aa t dh 1 0 1 0 a 2 a 1 a 8 r/w cat24c0 5 1 0 1 0 a 2 a 1 a 0 r/w cat24c0 3
CAT24C03/05 6 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice write operations byte write in byte write mode, the master sends the start condi - tion and the slave address with the r/ w bit set to zero to the slave. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the CAT24C03/05. after re - ceiving another acknowledge from the slave, the master transmits the data byte to be written into the addressed memory location. the CAT24C03/05 device will acknowl - edge the data byte and the master generates the stop condition, at which time the device begins its internal write cycle to nonvolatile memory (figure 5). while this internal cycle is in progress (t wr ), the sda output will be tri-stated and the CAT24C03/05 will not respond to any request from the master device (figure 6). page write the CAT24C03/05 writes up to 16 bytes of data in a single write cycle, using the page write operation (fig - ure 7). the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the data byte is transmitted, the master is allowed to send up to ?fteen additional bytes. after each byte has been transmitted the CAT24C03/05 will respond with an acknowledge and internally increments the four low order address bits. the high order bits that de?ne the page address remain unchanged. if the master transmits more than sixteen bytes prior to sending the stop condition, the address counter wraps around to the beginning of page and previously transmitted data will be overwritten. once all sixteen bytes are received and the stop condition has been sent by the master, the internal write cycle begins. at this point all received data is written to the CAT24C03/05 in a single write cycle. acknowledge polling the acknowledge (ack) polling routine can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, the CAT24C03/05 initiates the internal write cycle. the ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the CAT24C03/05 is still busy with the write opera - tion, noack will be returned. if the CAT24C03/05 has completed the internal write operation, an ack will be returned and the host can then proceed with the next read or write operation. hardware write protection with the wp pin held high, the upper half of memory is protected against write operations. if the wp pin is left ?oating or is grounded, it has no impact on the op - eration of the CAT24C03/05. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the ?rst data byte (figure 8). if the wp pin is high during the strobe interval, the CAT24C03/05 will not acknowledge the data byte and the write request will be rejected. delivery state the CAT24C03/05 is shipped erased, i.e., all bytes are ffh.
CAT24C03/05 7 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 7. page write sequence figure 6. write cycle timing a c k a c k a c k s t o p s a c k a c k s t a r t p sla ve address n = 1 p 15 address byte data byte n data byte n+1 data byte n+p bus activity: master slave t wr st op condition st ar t condition address ac k 8 th bi t byte n scl sd a figure 5. byte write sequence address byte data byte sla ve address s a c k a c k a c k s t o p p s t a r t bus activity: master slave a 7 a 0 d 7 d 0 figure 8. wp timing 1 8 9 1 8 a 7 a 0 d 7 d 0 t su:w p t hd:w p address byte data byte scl sda wp
CAT24C03/05 8 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice read operations immediate read upon receiving a slave address with the r/ w bit set to 1, the CAT24C03/05 will interpret this as a request for data residing at the current byte address in memory. the CAT24C03/05 will acknowledge the slave address, will immediately shift out the data residing at the current address, and will then wait for the master to respond. if the master does not acknowledge the data (noack) and then follows up with a stop condition (figure 9), the CAT24C03/05 returns to standby mode. selective read selective read operations allow the master device to select at random any memory location for a read opera - tion. the master device ?rst performs a dummy write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the CAT24C03/05 acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the CAT24C03/05 then responds with its acknowledge and sends the requested data byte. the master device does not acknowledge the data (noack) but will generate a stop condition (figure 10). sequential read if during a read session, the master acknowledges the 1 st data byte, then the CAT24C03/05 will continue transmitting data residing at subsequent locations until the master responds with a noack, followed by a stop (figure 11). in contrast to page write, during sequential read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page).
CAT24C03/05 9 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 11. sequential read sequence a c k a c k a c k s t o p n o a c k a c k p sla ve address data byte n data byte n+1 data byte n+2 data byte n+x bus activity: master slave figure 10. selective read sequence sla ve s a c k n o a c k s t o p p s t a r t s a c k sla ve address a c k s t a r t data byte address byte address bus activity: master slave figure 9. immediate read sequence and timing scl sd a 8 th bit st op no ac k da ta out 8 9 sla ve address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave
CAT24C03/05 10 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 300 mil wide plastic dip (l) a e b e1 b2 l a2 a1 e d eb 24c16_8-lead_dip_(300p).eps symbol a a1 b b2 d e e1 e eb l mi n 0.38 0.36 9.02 7.62 6.09 6.35 7.87 0.115 0.130 0.150 nom 0.46 1.77 1.14 7.87 2.54 bs c max 4.57 a2 3.05 3.81 0.56 10.16 8.25 7.11 9.65 notes: 1. all dimensions are in millimeters. 2. complies with jedec standard ms001. 3. dimensioning and tolerancing per ansi y14.5m-1982
CAT24C03/05 11 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 150 mil wide soic (w) 24c16_8-lead_soic.eps symbol a1 a b c d e e1 h l mi n 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 nom 0.25 0.19 max 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 bs c 0.50 1.27 1 0 8 e e1 d a1 e l 1 c b h x 45 a notes: 1. all dimensions are in millimeters. 2. complies with jedec speci?cation ms-012 dimensions. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C03/05 12 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead tssop (y) 8 5 1 4 e e1 e/ 2 pin #1 ident. d b l 1 e a a1 a2 see detail a see detail a seating plane c gage plane 0.25 symbol a a1 a2 b c d e e1 e l 1 mi n 0.05 0.80 0.09 2.90 6.30 6.4 4.30 0.00 8.00 nom 0.90 0.30 0.19 3.00 4.40 0.60 0.75 0.50 max 1.20 0.15 1.05 0.20 3.10 6.50 4.50 0.65 bs c notes: 1. all dimensions are in millimeters. 2. complies with jedec speci?cation mo-153. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C03/05 13 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-pad tdfn 2x3 package (vp2) e2 a2 e pin 1 index area l tdfn2x3 ( 03 ) .e ps a3 pin 1 id e b a1 3 x e d2 d a symbol a a1 a2 a3 b d d2 e e2 e l mi n 0.70 0.00 0.45 0.20 1.90 1.30 1.40 2.90 1.20 0.20 0.30 0.40 nom 0.75 0.02 0.55 0.20 re f 0.25 2.00 3.00 0.50 typ max 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 1.30 notes: 1. all dimensions are in millimeters. 2. complies with jedec speci?cation mo-229. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C03/05 14 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 5-lead tsot-23 (td) a2 a a1 d e b e e1 e1 e e1 l2 gauge plane l l1 c 5 lead tso t- 23 p ackage max 1.0 0.1 0.9 0.45 0.20 0.50 8 nom 0.05 0.87 0.15 2.90 bsc 2.80 bsc 1.60 bsc 1.90 bsc 0.40 0.25 bsc mi n 0.01 0.80 0.30 0.12 0.30 0 symbol a a1 a2 b c d e e1 0.95 bsc e e1 l 0.60 ref l1 l2 notes: 1. all dimensions are in millimeters. 2. complies with jedec speci?cation mo-193. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C03/05 15 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice package marking note: (1) the circle on the package marking indicates the location of pin 1. ymrf 24cxxi 8-lead tssop 8-lead pdip 8-lead soic fyyww r 24cxxwi fyyww r 24cxxli csi = catalyst semiconductor, inc. xx = device code (see marking code table below) i = temperature range yy = production year ww = production week r = product revision (see marking code table below) f = lead finish 4 = nipdau 3 = matte-tin csi = catalyst semiconductor, inc. xx = device code (see marking code table below) i = temperature range yy = production year ww = production week r = product revision (see marking code table below) f = lead finish 4 = nipdau 3 = matte-tin y = production year m = production month r = die revision (see marking code table below) xx = device code (see marking code table below) i = temperature range ww = production week f = lead finish 4 = nipdau 3 = matte-tin device code xx product revision r 24c03 03 g 24c05 05 j marking codes
CAT24C03/05 16 doc. no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice package marking 8-pad tdfn xx = device code matte-tin nipdau 24c01 ep ee 24c02 er eb 24c04 es ec 24c08 et ed 24c16 eu dz n = traceability code y = production year m = production month x x n n n n y m notes: (1) the circle on the package marking indicates the location of pin 1. (2) for tdfn and tsot packages, the product revision marking is included in the device code (xx). 5-lead tsot xx = device code matte-tin nipdau 24c01 ra mm 24c02 rb mn 24c04 rc mp 24c08 rd mr 24c16 re ml y = production year m = production month xxym xx = device code matte-tin nipdau 24c03 rev. g rk rh 24c05 rev. j rl rj y = production year m = production month xx = device code matte-tin nipdau 24c03 rev. g fa em 24c05 rev. j fb en n = traceable code y = production year m = production month
CAT24C03/05 17 doc no. 1116, rev. b ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice example of ordering information notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead ?nish is nipdau pre-plated (ppf) lead frames. (3) the device used in the above example is a CAT24C03yi-gt3 (tssop, industrial temperature, nipdau, tape & reel). (4) for additional package and temperature options, please contact your nearest catalyst semiconductor sales of? ce. prefix device # suffix 24c03 y i t3 product number 24c03 24c05 g C cat temperature range i = industrial (-40 c to +85 c) company id t: tape & reel 3: 3000/reel package l: pdip w: soic, jedec y: tssop vp2: tdfn td: tsot lead finish g: nipdau blank: matte-tin
catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 1116 revison: b issue date: 08/01/06 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ? ae 2 ? minipot? catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability arising out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. products with data sheets labeled advance information or preliminary and other products described herein may not be in production or offered for sale. catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing orders. cir cuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date document revision comments 03/08/06 doc# 1113 rev. a doc# 1114 rev. a cat24cat03 data sheet initial issue cat24cat05 data sheet initial issue 07/24/06 doc# 1116 rev. a combine CAT24C03 and cat24c05 data sheets into one data sheet. update marking and ordering information. 08/01/06 doc# 1116 rev. b update package marking

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